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32KiB ought to be enough for anybody

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@tenshi left/nasu/noodle/orca combined together are about 32kb

@tenshi

Hmm, how much can be cut from this for video memory... I'm thinking for 4 color dots.
256x256x2/8 = 16384

There is no more memory left for the shadow screen so updating large areas of the screen will be accompanied by flickering.

But without the screen, 32K is quite enough:)

@yrabbit when I tooted this I was taking stances on how my computer memory subsystem was going to be structured. The computer has three memory banks: ROM (program code), RAM (main memory) and STACK (dedicated stack memory).
Originally I wanted to make these three fully addressable (which meant taking 2 bits from addresses, leaving me with 2^14=16K addresses). 16K 16-bit words is 32KiB (!)

@yrabbit
Then I realized addressing stack is not really useful (plus that's an attack vector in buffer overflows!), since it can be manipulated using dedicated POP/PUSH instructions. As for ROM, not making it addressable would vastly simplify CPU design, however copying static data to memory (think, image bitmaps, etc.) could be cumbersome and slow... I'm still thinking on what to do with it :P
So finally this leaves 64Kx16=128KiB of addressable memory!

@tenshi
Well you can always have a special register which maps the ROM/RAM pages to the window in the address space, so that rom->ram copying is either completely eliminated or becomes just memory->memory MOV.

Just kidding, I'm a total ignoramus of processor architecture:)

@yrabbit Being a very simple RISC CPU, your memory-memory MOV is more like:

li r0, 0xDEAD # address DEAD to r0
li r1, 0xBEEF # value BEEF to r1
st r0, r1 # store 0xBEEF in address 0xDEAD

Which (I estimate) is way beyond the 6 cycles per word (!) mark...

So yeah, I'll have to take care of that somehow...

@tenshi
Well, yes, I think in terms of PDP11🤣

mov #len, R2
lbl: mov (R0)+, (R1)+
sob R2, lbl

@tenshi
I should note that such a range for the stack would be overkill:)

@yrabbit Yep. In the end I decided to make it a separate memory subsystem on its own, with a smaller memory chip and a 8-bit address register (I hope no one needs more than 255 recursion levels!)

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